Reference is made to ceding application Ser. No. 08/515,921, tided. xe2x80x9cWell Resistor for ESD Protection of CMOS Circuitsxe2x80x9d filed Aug. 16, 1995 and assigned to the same assignee as the present invention, and which is hereby incorporated by reference.
The present invention relates to a semiconductor structure for shunting current during an electrostatic discharge event in a semiconductor chip, and in particular to the use of well resistors to increase the resistance of the structure.
In conventional CMOS processes, built-in resistors from the active areas of a transistor protect transistors designed to shunt current by absorbing a portion of voltage drops, and also serve to limit the total amount of current that is allowed to flow during electrostatic discharge (ESD) events. ESD transistors are used to provide a known current path to discharge the current associated with ESD events. However, in processes where the resistance of the active areas of transistors is small, or is reduced to improve the frequency response of CMOS circuitry, the active area resistance no longer functions to provide such a current limiting effect through the ESD transistor. A need exists to add back in resistance to limit the current through ESD transistors during ESD events to prevent damage to such transistors and other semiconductor structures.
The present invention provides an apparatus for limiting the amount of current flowing through ESD transistor during an ESD event. Well resistors are coupled in series with the active areas of a field effect transit and conductors used to transport signals to and from a die.
In one embodiment of the present invention, an ESD transistor has n-well resistors formed beneath its n+ active areas. N+ active areas are further formed adjacent to each of the ESD transistor active areas, with the well resistor extending under at least a portion of such adjacent n+ areas. The n-well resistors and n+ areas are coupled electrically in series, so that current flowing through the ESD transistor also encounters the resistance of the n-well resistor which has a much higher sheet resistance than the n+ active areas. In one embodiment the sheet resistance of the n-well resistors is many tiles greater than that of the n+ active areas because the n+ active areas are covered with a silicide formed with tungsten or titanium to reduce the overall resistance of tie n+ active areas, which results in faster switching times for the transistor. Metal conductors are formed over the adjacent n+ areas, and are separated therefrom by an insulative layer formed of silicon dioxide, BPSG or other suitable insulator.
The metal conductors serve as conductors to the I/O pads and to the power supply, and have a plurality of contacts formed therethrough extending down into electrical contact with the n+ active areas. Further sets of contacts are formed in the ESD transistor n+ active areas. A metal layer is also formed on top of each set of the contacts for connection to other circuitry.
The n-well resistors provide large voltage drops during high currents, limiting both voltage and current experienced by the ESD transistor. Thus the adverse impact of ESD events is limited